The present invention relates generally to a semiconductor device, and more particularly to a clock synchronization circuit and a clock synchronization method which generate an internal clock synchronized to an external clock.
In general, a synchronous semiconductor device operating in synchronization with a clock from an external system (hereinafter, “the external clock”) includes a clock synchronization circuit in order to generate an internal clock of the semiconductor device (hereinafter, “the internal clocks”) having the same phase as the external clock. As the clock synchronization circuit, a phase locked loop (PLL) and a delay locked loop (DLL) have been widely used.
The phase locked loop is to synchronize a phase of the internal phase with a phase of the external phase, and the delay locked loop is to synchronize the internal clock with the external clock by reflecting on the internal clock a negative delay corresponding to a delay component in a clock path of the external clock generated within the semiconductor device.
Meanwhile, the semiconductor device enters into a power-down mode when there is no access to memory cells for the purpose of low power, in which it is allowed to reduce current consumption as possible by disabling the clock synchronization circuit. Further, when the semiconductor device exits into an active mode, the clock synchronization circuit is enabled again.
Hereinafter, although the clock synchronization circuit is shown as a delay locked loop for the purpose of easiness of explanation, it should be understood that other clock synchronization circuit including a phase locked loop can be applied.
Referring to FIG. 1, a delay locked loop circuit 1 according to prior art comprises a input buffer 10 buffering and inputting an external clock ECLK, a clock enable unit 12 selectively inputting an input clock ECLK1 output from the input buffer 10 by power-down signal PWDN, a phase updating unit 14 outputting an internal clock ICLK synchronized to the external clock ECLK by updating a phase of a reference clock ECLK2 output from the clock enable unit 12, and an output buffer 16 outputting data synchronized to the internal clock ICLK output from the phase updating unit 14.
Herein, the phase updating unit 14 comprises a phase delay unit 20 inputting the reference clock ECLK2 and delaying a phase of it to output the internal clock ICLK synchronized to the external clock ECLK, a delay model unit 26 modeling the internal clock ICLK with delay elements of the clock signal within the memory to output a feedback clock FBCLK, a phase comparing unit 24 inputting the reference clock ECLK2 and the feedback clock FBCLK and detecting a phase difference between two clocks input to output a phase detect signal DET, and a delay control unit 22 inputting the phase detect signal DET and outputting a control signal CTL which controls the phase delay of the phase delay unit 20.
Referring to FIG. 2, the operations of the conventional delay locked loop circuit 1 will be described. When the semiconductor device enters into the power-down mode, a power-down signal PWDN is enabled thus transitioning from logic low to logic high. Then, the delay locked loop circuit stops a phase update operation to save current states and store the previous locking information, thereby entering into a frozen state.
Herein, the phase update means keeping track of a phase difference between the feedback clock FBCLK and the reference clock ECLK2 in the delay locked loop circuit, and the frozen state means storing the previous locking information but updating the phase.
Meanwhile, the power supply voltage VDD can have voltage sections V1, V2 of which voltage level is randomly varied due to power noise. Such power noise continues to be generated even while the delay locked loop circuit remains in the power-down mode.
Conventionally, since the delay locked loop circuit has other locking information value in accordance with a level of power supply voltage VDD, the locking information value varies considerably if a level of the power supply voltage VDD of when the delay locked loop circuit enters into power-down mode and a level of the power supply voltage VDD of when the delay locked looped circuit exits the power-down mode are different to each other.
However, since prior delay locked loop circuit does not perform a phase update operation in response to changes of the power supply voltage VDD while remaining in the power-down mode, if it exits the power-down mode at power supply voltage level other than a level of power supply voltage VDD of when entering into the power-down mode, e.g., voltage section V1 or V2, a delay of the reference clock ECLK2 is controlled by the locking information un-updated, thereby generating the internal clock ICLK.
As a result, there is a problem that the semiconductor device cannot receive/transmit available data since a phase difference between the external clock ECLK and the internal clock ICLK is caused.